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发明名称
VERIFICATION PATTERN UTILIZING SYSTEM FOR LOGIC CIRCUIT
摘要
申请公布号
JPH02191067(A)
申请公布日期
1990.07.26
申请号
JP19890012654
申请日期
1989.01.20
申请人
NEC CORP
发明人
SHIMA NOBUO;TAKAGI KAZUHIKO
分类号
G06F17/50
主分类号
G06F17/50
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代理人
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