Assist circuits for SRAM testing

摘要

Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist techniques improve read stability and write margin of SRAM core-cells, respectively, when the memory operates at a lowered supply voltage. Assist circuits are activated at particular points in the memory cell circuit. The assist circuits are selectively activated for modifying the voltage along particular circuit elements to identify the potential defects that might be otherwise masked until substantially large. A March test invokes elements for activating the assist circuits to identify defects and indicate functional fault models (FFMs) associated with the defects.

主权项

1. A method of testing memory designs comprising:
identifying potential defects in a memory cell; defining a circuit for the memory cell, the circuit including resistance values indicative of the identified potential defects; providing an assist circuit, the assist circuit reducing voltage for detecting resistive-open or resistive-bridging defects in the memory cell, the assist circuit introducing a resistive value into the circuit for reducing voltage at predetermined points in a testing phase; and activating the assist circuit during a test cycle for detecting a resistive value corresponding to a defect.