| 摘要 |
PURPOSE: To reduce the storage capacity by connecting the output of each read amplifier, which corresponds to the most significant bit of each value, to a corresponding bit of a related adder and connecting other most significant input bits to all inputs. CONSTITUTION: Each line has a continuous partial product of variable word length. Since the word length is uniform in circuits on the outside of a memory M, it is necessary that bits deleted from words are added at the exit of the memory M to extend the reduced words. When 2's complement expression is selected for the partial product, the most significant bit of the word is repeated several times until the standard word length is obtained. A sum total Nb of required non-zero bits is Nb=b0 T-T<2> /4 where T is the number of coefficients and b0 indicates the precision of the center coefficient. Thus, the number of one-bit cells is reduced by T<2> /4, and it is reduced by 2N×T<2> /4 in the whole of a 2N-line memory. |
