| 摘要 |
In a data processing system with a central processing unit having a pipelined mode of operation, apparatus and method are disclosed for synchronizing the operation of a coprocessor unit with the remainder of the central processing unit, the remainder of the central processing unit being implemented for pipelined execution of instructions. Because the coprocessor unit performs manipulations of logic signal groups that require a longer time for execution than the manipulation contemplated by the requirements of pipelined instruction execution, the coprocessor unit must be synchronized with an instruction stream adapted to use the rigidly controlled pipelined implementation. In order to synchronize the coprocessor unit with the remainder of the central processing unit, the instructions controlling the operation of the coprocessor unit have two portions. A first portion of a coprocessor instruction designates the storage location into which the result of the previous operation is to be stored, while the second portion of the coprocessor instruction defines the operation to be performed on the operand in a designated location. |
