Overlay sampling methodology

摘要

One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.

主权项

1. A method of wafer alignment, comprising:
defining a layout-based wafer map by determining designed locations of a plurality of alignment structures with a layout tool; obtaining a measured surface topography of a wafer surface of a wafer as a function of wafer position with a surface measuring tool; defining a modeled wafer map comprising modeled alignment structure locations by projecting the layout-based wafer map onto the measured surface topography; defining a measured wafer map comprising measured alignment structure locations by measuring a subset of alignment structure locations on the wafer with an alignment tool; and adjusting the measured wafer map and the modeled wafer map to minimize disagreement between the measured alignment structure locations and the modeled alignment structure locations.