| 摘要 |
PURPOSE:To speed vector operation by outputting a relational operation result as a false output if the condition part of a conditional operation instruction is false when the operation result is used as the condition part of the instruction. CONSTITUTION:A write signal WE is outputted at every time even in case of a conditional operation instruction, and AND gates G1 and G2, and an OR gate G3 are provided. Therefore, in conditional relational operation, a decoder output VCSD comes to ''1'', the gate G1 is closed, and the gate G2 selects a comparison result as it is when a mask Mi is ''1'', thereby writing it in the comparison result Ci through the gate G3. In normal relational operation which is not conditioned, the output VCSD has ''0'' and the comparison result is written in the result Ci after being passed through the gates G1 and G3 as it is. When the mask Mi is ''1'', the comparison result Ci is set to ''0''. Therefore, when the comparison result Ci is used as the condition part of another conditional operation, the need for extra processing is eliminated. |
