| 摘要 |
PURPOSE: To allow a correct state to be set to a logic gate by forming a loop coupling, an access device, an inverter means, and a logic gate as a load with intersecting transistors. CONSTITUTION: Input terminals to logic gates 12 and 40 and an inverter 29 are connected with n-channel MOSFET. When a circuit point connected with the n-channel MOSFET input is switched by mistake from a logic state at a high voltage level to a logic state at a low voltage level, the n-channel transistors are temporarily switched to OFF state, until the reverse-biased drain area collecting generated electrons is charged by the circuit, so that the circuit point recovers the state of its former voltage level. However, since the first p-channel MOSFET, of which the output terminal is connected with drain, is always of an Off state, the output terminal keeps a same voltage as it had before being disturbed. Thus, an accurate logic state can be introduced into a feedback loop. |
