发明名称 MOSSHUSEKIKAIRO
摘要 PURPOSE:To utilize effectively a limited number of pins of a package by a method wherein different potential levels of at least two stages are given to one terminal and thereby the conditions corresponding to the number of stages are prepared inside an integrated circuit. CONSTITUTION:A terminal 102 which is an entrance for signals from the outside of an integrated circuit is connected to a signal line 101. A group 104 of inverters numbering N is constituted with the root of the ratio between beta of a P channel transistor and beta of an N channel transistor varied sequentially as alpha1- alphak-alphaN and, accordingly, with the logic level thereof varied as VGL1-VGLN, and the gates thereof are all connected to the signal line 101. Accordingly, some of the inverters numbering N can be made 1 and the others 0 by a voltage given to the terminal 102 from the outside, and thus conditions N+1, inclusive of the case when no potential is given from the outside, can be realized. Therefore, modes numbering N+1 can be selected by one terminal.
申请公布号 JPH0232590(B2) 申请公布日期 1990.07.20
申请号 JP19810149023 申请日期 1981.09.21
申请人 SEIKO EPSON CORP 发明人 HASHIMOTO MASAMI
分类号 G01R31/28;G01R31/317;G01R31/3185 主分类号 G01R31/28
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