发明名称 PARALLEL DATA PROCESSOR
摘要 PURPOSE:To efficiently execute shift processing by providing an A storage circuit and a B storage circuit for a processor and selecting and outputting the held data of the A storage circuit and the B storage circuit to a processor adjacent to the processor by the processor. CONSTITUTION:In the shift processing extending over pages, while an A storage circuit 21 is used for a relay for receiving input data from one adjacent processor and delivering the data to the other adjacent processor, a B storage circuit 22 is used for a saving destination for overflowed data. Further, only the processor positioned at the other edge of a page outputs the held data of the B storage circuit 22 so that saved data equivalent to data to be overflowed from the preceding page can be inputted from one edge of the page. Thus, the effective shift processing can be attained without adding an edge register to be the cause of the lowering of regularity.
申请公布号 JPH02184985(A) 申请公布日期 1990.07.19
申请号 JP19890003673 申请日期 1989.01.12
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KONDO TOSHIO;NAKAJIMA TAKATOSHI;TSUCHIYA TOSHIO
分类号 G06F15/16;G06F15/80 主分类号 G06F15/16
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