发明名称 ERRONEOUS SETTING PREVENTION CIRCUIT
摘要 PURPOSE:To prevent erroneous setting from being performed by holding preceding data as it is when an error is detected in data to be set. CONSTITUTION:When abnormality is detected in input C1-C6, a data abnormality detecting part 10 outputs a signal of HIGH level as the output. In such a state, the output of a gate 40 remains at the HIGH level even when a write pulse is inputted to the gate 40, and no leading edge of the write pulse at a time t1 is detected. Therefore, a memory keeps a preceding state at this time, and the output can also hold the preceding state. In such a way, the erroneous setting can be prevented from being performed.
申请公布号 JPH02184927(A) 申请公布日期 1990.07.19
申请号 JP19890005608 申请日期 1989.01.12
申请人 FUJITSU LTD 发明人 SHINOHARA AKIO
分类号 G06F11/00 主分类号 G06F11/00
代理机构 代理人
主权项
地址