| 摘要 |
<p>PURPOSE:To obtain fine gate length by forming a photo-resist layer having narrow line width, wrapping the photo-resist layer on a metallic deposit under the state, in which only one part of a top section is exposed, and shaping a gate electrode while using an Au plating layer, an opening of which is made smaller than the pattern width of the photo-resist layer, as a mask. CONSTITUTION:A photo-resist layer 11 is formed onto a semiconductor substrate 1, a first metallic deposit 12 capable of being plated with Au such as Ag onto the layer 11 and a second metallic deposit 13, in which an oxide film shaped onto a surface thereof prevents Au plating, such as Al onto the deposit 12. The metallic deposit 13 is patterned to a pattern 14 having narrow line width through etching using a photo-resist layer patterned through a Deep UV contact exposure method as a mask, an Au plating layer 15 is shaped onto the metallic deposit 12 under the state, in which the layer 15 is extruded to the periphery of the pattern of the second metallic deposit 13, through electrolytic plating, and a gate electrode 6 is shaped through a lift-off method while employing the Au plating layer 15 as a mask. Accordingly, the fine gate electrode of gate length of 0.5mum or less is acquired, and a GaAs FET having excellent high-frequency characteristics and high-speed workability is obtained.</p> |
