| 摘要 |
PURPOSE:To easily execute the debugging of fault processing by generating a pseudo fault when a memory writing address, which is executed from another device, is coincident with the contents of a pseudo fault address register. CONSTITUTION:A pseudo fault address register 10 holds an address value as a condition to activate pseudo fault generation and an output is compared with the memory writing address value from the other device by a comparator 30. When the coincidence is detected, an address coincidence signal is informed as '1'. When the value of an allowance flag 20 is in a pseudo fault generation allowable state, the address coincidence signal passes through an AND circuit 31 and a decoder 50 generates a pseudo fault signal. This signal is ORed with the fault detection signal of a real hardware register by an OR circuit 51 and a fault detection flag 60 is set to '1'. Then, the output of the flag 60 is informed of a fault processor as an error informing signal. Thus, the pseudo fault can be generated asynchronously with the self-device and the debugging of the fault processing function can be enough evaluated without man power. |
