发明名称 CHROMA SIGNAL NOISE REDUCTION CIRCUIT
摘要 PURPOSE:To effectively reduce noise with a simple constitution, by passing the same signal to a single delay circuit repetitively and blocking a signal passing in response to a vertical blanking pulse. CONSTITUTION:A color difference signal via low pass filters LPF1, LPF2 is multiplied with a prescribed coefficient at coefficient devices FM1, FM2 and given to adders ADD11, ADD12. An output of the adders ADD11, ADD12 is transmitted to modulators MOD1, MOD2 and delay circuits DL11, DL12 for a delay and inputted to coefficient devices FM3, FM4. The output of the coefficient devices FM3, FM4 is given to the adders ADD11, ADD12. In the adders ADD11, ADD12, the outputs of the FM1, FM3 and FM2, FM4 are summed, and a vertical blanking pulse is given to the FM1-FM4 to reduce the output level of the FM1-FM4 at the vertical blanking period.
申请公布号 JPS5844880(A) 申请公布日期 1983.03.15
申请号 JP19810143002 申请日期 1981.09.10
申请人 HITACHI DENSHI KK 发明人 HIRONO MASARU;ISHIBASHI SHIZUKA
分类号 H04N9/64 主分类号 H04N9/64
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