| 摘要 |
PURPOSE:To reduce the quantity of hardware by repeatedly connecting a unit circuit consisting of a switch means and a delay means. CONSTITUTION:One digit in a digit number with codes is expressed by a pair of bits which are coordinate in (n) bit registers in a first circuit 1 and a second circuit 2. Namely, -1, 0, +1 in respective digits of the digit number with the codes are respectively expressed by (1,0), (0,0) and (0,1). Here, the first and second bits in parentheses are set to be the bits which the (n) bit registers in the first circuit and the second circuit have. When a delay means 4 and a switch means 3 simultaneously and sequentially read the bits of two (n) bit registers 10 from the highest-order bit to the coordinate bits, the output of an OR means 20 in a circuit to which the (n) bit register 10 having the bit of zero in a higher-order belongs comes to '1' faster than the output of the other OR means. By detecting it, the pair of bits can be decided whether they are either (1,0) or (0,1), namely, the digit of non-zero in the highest-order is -1 or +1 as the digit number with codes. |
