| 摘要 |
PURPOSE:To increase the margin of a wiring region by maintaining the value of a plurality of resistance values in a basic cell in integer times relationship and composing the resistor in the logic circuit of a macrocell by the connection of the resistor belonging to the basic cell, thereby simplifying the wiring pattern. CONSTITUTION:Resistors in basic cells 16, 17 have a relation of R1=R4=2R2= 4R3, and the resistor between the collector of an input transistor in a TTL logic circuit of a macrocell having two basic cells 16, 17 and a power source voltage Vcc is connected via 42 in parallel with the R4 belonging to the basic cells. Accordingly, related wirings 41, 42, 43 are formed of the first wiring layer, it is not necessary as the conventional one to utilize the second wiring layer, a through hole is not necessary for the wiring region for forming the macrocell, thereby simplifying the wirings, avoiding the unbalance of the circuit operation due to the alleviation of the current concentration and forming a margin for the wiring region 28. Thus, other wirings 44, 45 can be formed, thereby increasing the degree of freedom of wirings. |
