| 摘要 |
PURPOSE: To provide a low-noise, wide-band, and high-speed precise frequency synthesizer by effectively coupling a phase locked loop(PLL) to a frequency locked loop(FLL) and giving such constitution that a maximum operation point of the coupled loop may be kept. CONSTITUTION: The output of a VCO 11 is subjected to frequency division in an N frequency division block 13 by a selectable number N to generate an input signal to a PLL phase detector 15. This detector 15 compares this input signal with a prescribed reference signal to generate an error signal which has a voltage proportional to the phase difference, and a PLL tuning signal is given to the VCO 11 through a PLL filter 17 and a PLL gain amplifier 19. Further, the FLL including a delay line discriminator 10 which sends back a frequency control signal (VCO tuning signal) through a line 34 is included, and the output of the gain amplifier 19 is coupled to a variable phase network 25 of the frequency discriminator 10 by a line 18, and phase shift of the variable phase shift network 25 is adjusted by the PLL tuning voltage to compensate the change of the output frequency of the VCO 11. |
