发明名称 CLOCK FREQUENCY ADJUSTMENT METHOD FOR DATA RECEIVER
摘要 <p>PURPOSE:To prevent the occurrence of an idle buffer or an occupied buffer by adjusting a frequency of a readout clock in response to the frequency differ ence between a write clock and the readout clock. CONSTITUTION:When an oscillated frequency of a VCO 5 is lowered and a count of an up-down counter 6 exceeds +x, an output of a ROM 7 is accumulat ed to a voltage outputted before the excess in the increasing direction and an output of an integration device 8 is increased. The oscillated frequency of the VCO 5 is increased accordingly and the count of the counter 6 is corrected so as to be within a range of '-x or over and +x or below'. When the oscillated frequency of the VCO 5 is increased and the count of the counter 6 exceeds -x, the output of the ROM 7 is accumulated to the voltage outputted before the excess in the decreasing direction and the output of the integration device 8 is lowered. The oscillated frequency of the VCO 5 is decreased accord ingly and the count of the counter 6 is corrected so as to be within a range of '-x or over and +x or below' similarly.</p>
申请公布号 JPH02179045(A) 申请公布日期 1990.07.12
申请号 JP19880333150 申请日期 1988.12.28
申请人 VICTOR CO OF JAPAN LTD 发明人 YAMAGISHI TORU
分类号 H04L7/00 主分类号 H04L7/00
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