发明名称 MEMORY ACCESS CONTROLLER
摘要 <p>PURPOSE:To access a memory at a high speed with a simple constitution by starting the access with a false address strobe signal generated by a cycle start signal. CONSTITUTION:An access control part 6 is provided, and a cycle start signal ECS and an address strobe signal AS are inputted from an MPU 1 to the control part 6, and the control part 6 generates a pseudo address strobe signal F-AS and a cycle effective signal VLD-CYC and gives them to a DRAM controller 2. The access control part 6 consists of a sequencer or the like. The access is started with the pseudo address strobe signal F-AS. Thus, the memory is accessed at a high speed with the simple constitution.</p>
申请公布号 JPH02178858(A) 申请公布日期 1990.07.11
申请号 JP19880334363 申请日期 1988.12.29
申请人 YOKOGAWA ELECTRIC CORP 发明人 KAWADA YASUNORI
分类号 G06F12/08;G06F15/78 主分类号 G06F12/08
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