Split bus multiprocessing system with data transfer between main memory and caches using interleaving of sub-operations on sub-busses

摘要

In a data processing system in which a plurality of data processing units, as well as the main memory unit, are coupled to a system bus, the utilization of the system bus can be increased to such an extent that each of a plurality of cache memory units coupled to the system bus can have a plurality of data processing units coupled thereto. The system bus utilization is increased by dividing the system bus access operation into a plurality of sub-operations and by providing a defined cyclic sequence for the cache memory units to have access to the system bus. The system bus is divided into a plurality of sub-bus units to handle separate functions of data transfer. The main memory unit has apparatus for efficient execution of the write-modify-read operation. In addition, the cache memory units can be divided in a plurality of sub-units and the access to the system bus arranged in terms of cyclic access of the cache memory subunits.