| 摘要 |
A method and apparatus for performing high performance multiplication in a computer central processor unit which implements a sliced design configuration. Each slice changes its "personality" by virtue of receiving consecutive bits of the multiplicand. The receipt of consecutive bits by each slice eliminates the need for the interconnection of successive slices in separate chips. Thus, the apparatus allows the avoidance of significant timing delays, inherent in such interchip connections, which diminish computer system multiplication performance, and allows the multiply cycle time to be as fast as a latch-to-latch transfer across chips.
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