发明名称 Bit map display apparatus for performing an interruption display among planes at high speed
摘要 A bit map display apparatus of this invention includes a bit map memory consisting of a plurality of memory planes, a display controller which can output a window number indicating a displaying window in accordance with display scan, a register, arranged for each plane, for holding bit data for designating a display enable/disable state in units of windows, a selector, arranged for each plane, for selecting one bit of output data from the corresponding register as a mask bit in accordance with the window number indicated by the display controller, and a gate circuit, arranged for each plane, for controlling data read out from the corresponding plane in accordance with the mask bit.
申请公布号 US4940971(A) 申请公布日期 1990.07.10
申请号 US19880238222 申请日期 1988.08.30
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 HASEBE, KOUKI
分类号 G06F3/048;G06F3/14;G06T11/20;G09G5/14 主分类号 G06F3/048
代理机构 代理人
主权项
地址