发明名称 CLOCK DUTY COMPENSATING CIRCUIT
摘要 PURPOSE:To always obtain an output signal of duty 50%, by comparing the sine wave signal with the threshold voltage to actuate a switch with the output signal of the comparison and charging/discharging an integral capacitor to use the terminal voltage of the capacitor to the threshold value. CONSTITUTION:A sine wave signal given from an oscillator OSC having the same frequency as the desired clock frequency is applied to a comparator COMP to be compared with the threshold voltage of the output of an integration circuit INT. Then a clock is delivered through an output terminal OUT of the COMP to control a switch circuit SW. While the clock is set at 1, the SW changes the capacitor C of the circuit INT with the voltage V. While the clock is set at 0, the SW is set at the voltage -V to discharge the electric charge of the capacitor C. When the threshold voltage level of the COMP is set at L1, the discharging time is longer than the charging time of the capacitor C with <=50% duty. Then the threshold level is lowered gradually down to the 50% duty. The duty is set at >=50% when the threshold level is set at L3. And the 50% duty is obtained by reversing the above-mentioned process.
申请公布号 JPS5847324(A) 申请公布日期 1983.03.19
申请号 JP19810145757 申请日期 1981.09.16
申请人 FUJITSU KK 发明人 KARIBE HIROHISA
分类号 H03K5/08 主分类号 H03K5/08
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