| 摘要 |
PURPOSE:To sharply reduce the minimum value of the lag time for the titled integrated circuit while the lag time for power consumption is being maintained at a small value by a method wherein, in the application of an I<2>L gate, a vertical type transistor is composed of the high-density first region of first conductive type, the first region of second conductive type and the third region of first conductive type. CONSTITUTION:Within the partial region 3' of the N type region 3 which was surrouded by a P type region 4, an ion is introduced from the surface by performing ion implantation or the diffusion subsequent to the ion implantation, for example, an N type region 6 is provided adjacent to or in the vicinity of a P type region 2, and the impurity density of the N type region is made higher than that of the N type region 3. when the gate I<2>L wherein the NPN transistor constituted as above is compared with one having no N type region 6, the munimum value of lag time can be improved remarkably without increasing the lag time product. |
