| 摘要 |
PURPOSE:To reduce the scale of an address buffer circuit, by securing the synchronism just with a latch signal for a clock synchronizing C-MOS address buffer circuit having the reduced power consumption. CONSTITUTION:A clock synchronizing C-MOS address buffer circuit contains a first stage inverter 1, the next stage inverter 2 and an FF3. The power consumption of such buffer circuit is reduced with use of the latch signal that activates the inverter 1 only for a period during which the input address signal AIN is latched. Furthermore this latch signal is used to secure the clock synchronism between the inverter 2 and the FF3. Then the mutual conductance of the transistors forming the inverter 2 is set larger than that of the transistors forming the FF3 to assure the latching action of the FF3. In such way, the synchronism is secured only with the latch signal. This can reduce the scale of an address buffer circuit. |
