| 摘要 |
PURPOSE:To elevate a degree of integration, by selectively applying the supply voltage in accordance with the operation mode, to a memory matrix part of an RAM, a bit line selecting circuit separated from a well area of a word line selecting circuit, and a well area of other logical circuit. CONSTITUTION:A circuit 1 is constituted of an FF circuit consisting of p-channel MISFETs Q1, Q2 and n-channel MISFETs Q3, Q4, and n-channel transmission gate MISFETs Q5, Q6. A work line selecting circuit constituted of an inverting circuit consisting of a memory cell, a p-channel MISFET Q7, and an n-channel MISFET Q8, and a Y-address decoding circuit YD, a bit line selecting circuit constituted of MISFETs Q9, Q10 of a circuit 2, inverting circuits Q11, Q12 and an X-address decoding circuit XD, an input/output circuit I/O, and a P type well area for forming an n-channel MISFET in a logical circuit LGC are separated from each other and are constituted. To the well area of the circuit 2 side, negative supply voltage -VDD is supplied selectively in accordance with the operation mode. |
