发明名称 PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To expand range of the acquisition of synchronizm by prefixing N bits in the same logical condition at the code bit of a digital signal at K bits, adding '+1' when a phase changes from a second quadrant to a third quadrant, and adding '-1' in an opposite case. CONSTITUTION:A converting ROM 7 outputs a digital signal at K=eight bits indicating phase information to a quadrant detector 8 and a same value bit adding circuit 14. A quadrant change detector 10 subtracts the output quadrant signal of a delay device 9 from the output quadrant signal of the quadrant detector 8. When the phase changes from a second quadrant to a third quadrant, the digital signal at N=four bits having the contents of '+1' is outputted, when the phase changes from the third quadrant to the second quadrant, the digital signal at four bits having the contents of '-1' is outputted, and in the other cases, the digital signal at four bits having the contents of '0' is outputted. Thus, since the chase comparing characteristic is not periodical, and it is proportional to the phase change, the range of the acquisition of synchronizm can be expanded.
申请公布号 JPH02170621(A) 申请公布日期 1990.07.02
申请号 JP19880324205 申请日期 1988.12.22
申请人 NEC CORP 发明人 ICHIYOSHI OSAMU
分类号 H03L7/085;H03L7/10 主分类号 H03L7/085
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