| 摘要 |
PURPOSE:To speed up parallel processing of data and its control by executing a total operation and a prefix sum operation for a packet to be asynchronously sent while it passes a MIN once. CONSTITUTION:Eight sets of processors PE0-PE7 are connected by an omega network to be one of representative multistage interconnection network (MIN: Multistage Interconnection Network), an two-input/two-output (2X2) switches 1-12 are provided. For values held in the eight sets of processors (PE), the prefix sum is calculated while they pass the MIN, the value is transferred to the PE, the operation to satisfy a connection role and a communication role such as an addition, an OR, an AND, a maximum and a minimum is executed, and the result is transferred to the PE of a designated address. Thus, the parallel processing of the data and the control can be made high-speed. |
