| 摘要 |
PURPOSE:To reduce the scale of the hardware by adding a pulse width detection circuit to a data replacement circuit of an asynchronous signal and revising a memory into a storage circuit. CONSTITUTION:A storage circuit 2 uses an address 7 of an address (m) and a write signal 9 synchronously with a data 8 to store said address 7 of address (m) and data 8. A comparator circuit 1 compares an address output signal 10 of the circuit 2 with an address signal 5 repetitively sequentially address 1-n. A pulse width detection circuit 3 detects it that the pulse width of an output signal 12 of the circuit 1 is l times of that of a reference clock 15. When the output signal 13 from the circuit 3 is inputted to the data replacement circuit 4, the circuit 4 replaces a data A at a terminal 6 in a relevant address and a data B at a terminal 8 based on the output signal 13 from the circuit 3. Thus, a level 1 of the A data input signal is replaced into a level 1 of the B data input signal and outputted to a terminal 14 of the circuit 4.
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