| 摘要 |
PURPOSE:To generate a data sampling clock without a phase error by generating the data sampling clock synchronizing with a frame synchronizing signal. CONSTITUTION:A latch circuit 12 latches the frame synchronizing signal from a main device, and a latch circuit 13 latches the out-put of the Q terminal of the latch circuit 12. A counter 10 is initialized by signals from the latch circuits 12 and 13, and a counter 11 is initialized by a carry signal from the counter 10 and the signals from the latch circuits 12 and 13, and they count the signal from a crystal oscillator 9, respectively. Therefore, the counters 10 and 11 output the signals synchronized with a comparatively slow frame synchronizing signal, and frequency dividers 14-17 output the data sampling clock synchronized with the frame synchronizing signal of frequency lower than that of a transmission clock, respectively. In such a way, it is possible to generate the data sampling clock without the phase error. |
