发明名称 PLO MONITORING CIRCUIT
摘要 PURPOSE:To attain the reduction of hardware quantity and the improvement of detecting accuracy by providing a mask circuit to generate a mask for detecting the abnormality of a PLO(phase locked loop oscillation circuit) and a D-FF(D flip-flop). CONSTITUTION:A mask waveform (b) of drift(constant phase error) specification width generated from the arbitrary output clock of a frequency divider 5 in the PLO at the mask circuit 6 in a PLO monitoring circuit is compared with an input signal waveform (a) at the D-FF 7. Since the mask waveform (b) cannot blanked by the input waveform (a) when the abnormality occurs in the drift of the PLO from the phase relation of the mask waveform (b) with the input waveform (a), the output waveform (c) of the D-FF 7 goes to an (L) level. Also, all the output clocks of the frequency divider 5 at the time of interruption of the output of the PLO go to the (LL) levels, and also, the mask waveform (b) that is the output of the mask circuit 6 goes to the (L) level, therefore, the output waveform (c) of the D-FF 7 also goes to the (L) level, then, the abnormality can be detected. In such a manner, since a circuit can be constituted of one detection circuit, the hardware quantity can be reduced, and also, it can be constituted of only digital circuits, the detecting accuracy can be improved.
申请公布号 JPH02166920(A) 申请公布日期 1990.06.27
申请号 JP19880320674 申请日期 1988.12.21
申请人 HITACHI LTD;HITACHI COMMUN SYST INC 发明人 YAMADA IZURU;TAMAKOSHI MASASHI
分类号 H03L7/095 主分类号 H03L7/095
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