| 摘要 |
PURPOSE:To align the phases of plural input clocks within the range of one cycle of a phase comparison clock by using a phase reference clock and the phase comparison clock in common. CONSTITUTION:A phase comparator 11 compares the phase of the input clock phiIN with frequency (f) with that of the phase reference clock phi1 with the same frequency (f), and outputs a pulse of phase comparison clock phi2 with frequency fn(n:arbitrary integer). A phase difference detection circuit 12 counts the number of pulses, and compares a counted value with a threshold value set in advance, and outputs a result by judging size relation for the threshold level. A delay quantity setting circuit 13 corrects a delay quantity corresponding to the above output, and outputs it as a binary parallel signal. A variable delay circuit 14 varies the delay quantity by the output of the circuit 13 and the phase comparison clock phi2, and performs the phase adjustment of the input clock phiIN in a direction to decrease the phase difference with the reference clock phi1. In such a manner, it is possible to adjust the phase of the input clock phiIN within the range of one cycle of the phase comparison clock phi2. |
