RESETTING CIRCUIT FOR MULTI-CPU SYSTEM

摘要

PURPOSE:To increase the rising speed of a multi-CPU system and at the same time to the fetching frequency of wrong data by resetting plural CPUs in sequence and with time lags at the starting of the system. CONSTITUTION:A power supply is applied at a time point t0, the charging voltage EC of a capacitor 25 gradually rises, and the output R1 of an comparator 21 rises up when the voltage exceeds the level of voltage V1 at a time point t1. Thus a CPU 11 is reset at the point t1. Then the voltage EC exceeds the level of voltage V2 at a time point t2. Thus the output R2 of a comparator 22 rises up and a CPU 12 is reset. Then a CPU 13 is reset at a time point t3 and a CPU 14 is reset at a time point t4 respectively. In such a way, the CPU 11-14 are reset in sequence in different timings at and after the point t0. Thus the collisions of communication requests are decreased and therefore the malfunctions to fetch the wrong data are also decreased for each CPU.