Single supply ecl to cmos converter.

摘要

An ECL to CMOS converter having a differential ECL clock input and an ECL data input is provided. A reference voltage is generated by averaging the level shifted differential ECL clock signals (CLOCK, CLOCK) using a voltage divider (26, 28). This reference voltage and the level shifted ECL data input are compared by a CMOS comparator (20) to provide a CMOS data output. The level shifters, comparators, and the voltage divider are integrated in a standard VLSI CMOS process that enables the resultant integrated circuit to operate from a single supply voltage.