| 摘要 |
<p>The present invention provides a circuit for delaying an input pulse in response to a control signal comprising: a first emitter-coupled-logic (ECL) noninverting stage (Q1, Q2, Q3) having an output terminal (B) and having an input terminal (A) for receiving the input pulse; a first delay-timing capacitor (C) coupled between the output terminal of the first ECL noninverting stage and a first supply voltage; a first delay-current source (Q6, RUi) coupled between the first ECL noninverting stage output terminal (B) and a second supply voltage, said first delay-current source having a control terminal (VR1) for varying its output current and the control terminal coupled to receive the control signal, with the fall time of a signal on the output terminal of the first ECL non-inverting stage being proportional to the control signal. The invention also provides a circuit for discriminating an input pulse width including such a delay circuit.</p> |
