| 摘要 |
PURPOSE:To reduce the variance of clocks and the skew of the clocks having respective phases by forming a means for executing the previously determined logical operation of an output from a prescribed stage of the 1st shift register and an output from a prescribed stage of the 2nd shift register. CONSTITUTION:A signal outputted from a reference clock oscillating circuit 1 is multiplied by a multiplying circuit 2, which outputs the 1st and 2nd multiplied clocks which have previously fixed phase difference. The 1st and 2nd multiplied clocks are inputted respectively to the 1st and 2nd n-stage shift registers 4, 5 for executing shifting operation synchronously with the reference clock. The reference clock is applied to the register 4 and a previously determined reference clock outputted from a delay element 3 is applied to the register 5. The previously determined AND of output signals 11-1-11-4 and output signals 12-1-12-4 outputted from the 1st 4th stages of the registers 4, 5 are found out by AND gates 6-1-6-4. Consequently, the variance of respective clocks is reduced and the skew of respective clocks in respective phases is reduced. |
