| 摘要 |
A data transfer apparatus (1) includes a plurality of channels (111 to 11n) and a transfer speed control circuit. A plurality of channels are connected to input/output devices (31 to 3n), respectively. Each channel number is assigned to the corresponding channel. The transfer speed control circuit is arranged between the channels and a memory (2). The transfer speed control circuit includes a monitor for monitoring a rate of data transfer from the input/output devices (31 to 3n) to the memory (2), and a controller for controlling and decreasing a difference in speed between data sent from the input/output devices (31 to 3n) and memory access when the monitor result represents a predetermined difference.
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