发明名称 SPEED VARIABLE TYPE CLOCK REGENERATION CIRCUIT
摘要 PURPOSE:To respond to a various kinds of transmission speed of modulation data by varying the frequency of a second VCO(voltage controlled oscillator), and mixing it with the output signal of a first VCO by a mixer. CONSTITUTION:A clock phase error signal extracted by a digital phase error extraction circuit 1 is passed through a loop filter 2, and a D/A converter 3, and the frequency and the phase of the first VCO 4 are controlled by the signal. Also, the second VCO 7 generates a various kinds of frequencies by a frequency control signal inputted from the outside. And the output signals from the first VCO 4 and the second VCO 7 are mixed by the mixer 5. Therefore, the frequency of a regenerating clock signal can be varied arbitrarily by varying the oscillation frequency of the second VCO 7 by an external frequency control signal. In such a way, it is possible to respond to the transmission speed of all the modulation data by one circuit.
申请公布号 JPH02166940(A) 申请公布日期 1990.06.27
申请号 JP19880322358 申请日期 1988.12.21
申请人 NEC ENG LTD 发明人 EGUCHI KUNIHARU
分类号 H03L7/08;H04L7/033 主分类号 H03L7/08
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