Visual signal processing backplane bus

摘要

A custom bus for a visual signal (image) processing system which can interface with a standard high speed industrial standard computer bus and requires minimal interface circuitry. Eight lines are dedicated to eight data/address bits which are supplied to a bidirectional I/O buffer on each VSP circuit card. A separate board select signal is supplied to each circuit card to enable the I/O buffer. Six bits on six lines provided to each VSP circuit card provide a signal selecting a particular device on each circuit card. Each circuit card contains a decoding circuit for decoding the device select signal and enabling an individual device on the card in response to the device select signal.