发明名称 CLOCK CONTROL CIRCUIT
摘要 <p>PURPOSE:To vary a duty and a skew in a processor by providing tri-state elements, and selecting a desired tri-state element and supplying an internal clock. CONSTITUTION:The tri-state elements 51a - 51c, and 52a - 52c output internal clocks phi1A and phi2A which differ in rising time and falling time from applied two-phase clocks phi1 and phi2. Desired tri-state elements are selected among those tri-state elements 51a - 51c and 52a - 52c with element selection signals ES1 - ES3 from an element selecting circuit 6 and the internal clocks phi1A and phi2A which are outputted by the selected tri-state elements 51a - 51c and 52a - 52c and varied in rising time and falling time are supplied to other internal circuits in the processor.</p>
申请公布号 JPH02165215(A) 申请公布日期 1990.06.26
申请号 JP19880319486 申请日期 1988.12.20
申请人 MITSUBISHI ELECTRIC CORP 发明人 TERAYAMA FUMIHIKO
分类号 G06F1/06 主分类号 G06F1/06
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