| 摘要 |
<p>PROGRAMMABLE HIGH-SPEED DIGITAL DELAY CIRCUIT A high-speed electrical circuit (10) provides an output signal that is a delayed version of a digital input signal. The circuit includes two subcircuits (20 and 22) which receive the input signal and whose outputs (52 and 56) are summed together. The subcircuits provide two different paths for the digital input signal to travel, one path providing a long time delay and the other path providing a short time delay. Each of the subcircuits comprises a pair of emitter-coupled transistors (24 and 26; 28 and 30). The subcircuit providing the long delay time includes transistors which have large areas and collector resistors that promote relatively slow transistor switching response time. The subcircuit providing the short delay time is optimized for high speed operation. An externally applied control signal controls the relative amounts of current flowing through the emitters of the pairs of emitter coupled transistors and thereby controls the proportion of the delay time effected on the digital input signal by each of the slow and fast paths. The total time delay provided by the circuit ranges from that of the slow path to that of the fast path. The control signal provides a means to maintain the desired amount of delay time should it change in response to changes in temperature.</p> |
