| 摘要 |
PURPOSE:To prevent a gate insulating film from being destroyed by a charge-up at an ion implantation operation and to enhance a yield by a method wherein an impurity concentration of a source region and a drain region of a MOSFET constituting a memory cell is made lower than that of other MOSFET's. CONSTITUTION:In a MOS-type memory integrated circuit device which contains a MOSFET constituting a memory cell and the other MOSFET, an impurity concentration of a source region and a drain region 5, 7 of the MOSFET constituting the memory cell is made lower than that of a source region and a drain region 10, 12 of the other FET. For example, a source region and a drain region 5, 7 of a MOSFET in a memory cell part of a MOS-type DRAM are formed by an ion implantation operation at a dose of 2 to 5X10<13>/cm<2> by using phosphorus is impurities; a source region and a drain region 10, 12 of a MOSFET constituting a peripheral circuit are formed by the ion implantation operation at a dose of 10<15> to 10<16>/cm<2> by using arsenic as impurities; impurity concentrations are set at 4 to 10X10<18>/cm<2> and 10<20>/cm<2> or higher, respectively. |
