发明名称 FRAME PROCESSING CIRCUIT
摘要 PURPOSE:To stop a propagation error through the use of a BPID when the propagation error takes place in a picture element code BPLX at the reproduction side by inserting an identification code BPID representing a picture block of a picture element code located at first in each SYNC block. CONSTITUTION:When an error takes place in the process of recording and reproduction, the write side cannot discriminate kinds of codes in an MBP slot. Thus, the readout side cannot recognize it how many bytes of BPLX are required for a picture block and then the propagation error of the BPLX is caused. The refreshing stopping the propagation error generated in the write and readout side is implemented by referencing the BPID. All the BPID are written in a memory block 8.0 in the write period by taking an effective SYNC block number as an address. At the start of readout, the BPID of the first effective SYNC block is read immediately from a memory block 80 and fed to a comparator circuit 135.
申请公布号 JPH02162981(A) 申请公布日期 1990.06.22
申请号 JP19880317737 申请日期 1988.12.16
申请人 SONY CORP 发明人 NAGAI MICHIO;SHIROTA NORIHISA
分类号 H04N5/92;H03M7/40;H04N7/24;H04N19/00;H04N19/115;H04N19/13;H04N19/132;H04N19/136;H04N19/137;H04N19/149;H04N19/176;H04N19/186;H04N19/196;H04N19/423;H04N19/46;H04N19/587;H04N19/59;H04N19/65;H04N19/66;H04N19/70;H04N19/85;H04N19/89;H04N19/895;H04N19/91;H04N19/98 主分类号 H04N5/92
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