发明名称 KOSOKUFUURIEHENKANNOENZANSOCHI
摘要 <p>PURPOSE:To decrease the multiplying frequency and to shorten the arithmetic time by performing a butterfly operation with high efficiency after sorting the phase revolution factors into two types requiring no multiplication and two types requiring mltiplication. CONSTITUTION:Both the real number part data AR and the imaginary number part data A1 are supplied to input terminals 1 and 2 respectively; while the real number part data BR and the imaginary number part data B1 are supplied to input terminals 3 and 4 respectively. These data select multipliers in accordance with the contents of an integer part P. That is, the input data of terminals 3 and 4 are selected and delivered as they are with no multiplication by changeover switches S1-S4 in the case of types 1 and 2 where P is ''0'' or ''2''. While the output data of multipliers 9-12 are selected and delivered in the case of types 3 and 4 where P is >=4. Thus a butterfly operation is carried out for the input data at the input side just with addition/subtraction when the value of the phase revolution factor requires no multiplication. If the multiplication is needed, the output data of the multiplier is delivered with switch. In such a way, the frequency is decreased and the arithmetic time can be shortened.</p>
申请公布号 JPH0228188(B2) 申请公布日期 1990.06.21
申请号 JP19830078824 申请日期 1983.05.04
申请人 VICTOR COMPANY OF JAPAN 发明人 TANAKA YOSHIAKI;INAMI MAMORU;OOTSUKI YOSHIKI
分类号 G06F17/14 主分类号 G06F17/14
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