发明名称 KEISANKISHISUTEMUNOSEINOCHOSEIHOHO
摘要 PURPOSE:To facilitate the control of performance of a computer system together with the expansion of a control range and to improve variable properties, by providing an interval register and a real time counter to designate both the start time and the stop time for control the start or stop time as well as the system performance. CONSTITUTION:A real time counter 5 is provided together with a start interval register 3 and a stop interval register 4. The counter 5 continues a count-up action up to the value designated by the register 3. Meanwhile a computer system is working. When the count value of the counter 5 reaches a level designated by the register 3, a control circuit 51 receives an access and clears the counter 5. Then the counter 5 continues its count-up action up to the value designated by the register 4. While the interlocking is applied to the pipeline of a CPU of the system. Thus the system is kept discontinued. Then the circuit 51 clears the counter 51 when the count value reaches the level shown by the register 4. Thus the counter 5 restarts its count-up action. This count-up action is repeated and therefore the start/stop of the CPU can be set in an optional cycle. Thus the system performance can be controlled with high flexibility.
申请公布号 JPH0227695(B2) 申请公布日期 1990.06.19
申请号 JP19850217076 申请日期 1985.09.30
申请人 FUJITSU LTD 发明人 FUJIOKA SHUNTARO;FUJIMAKI HIDEAKI
分类号 G06F11/22;G06F11/34 主分类号 G06F11/22
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