| 摘要 |
Apparatus for testing the electrical integrity of printed circuit boards under test (BUTs), each BUT having a plurality of downwardly directed accessible nodes, the apparatus including support apparatus for removably supporting the BUT, test circuitry including a plurality of upwardly directed channel nodes below the support apparatus, connection apparatus for electrically connecting the channel nodes to the BUT nodes, the connection apparatus comprising a universal board carrying probes in a universal grid pattern, means to activate selective probes, and a translator board to make electrical connection between upper and lower conductors in different patterns.
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