PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER

摘要

In an improved phase-locked loop frequency synthesizer, a voltage is continuously applied from a power source to a fixed divider and a programmable divider respectively composed of such lower electric power consuming means as C-MOS circuit such that the fixed and programmable dividers preserve the counting value thereof when the inputs are interrupted at the time of changing from a phase-locked loop to an open loop 80 that phase lock is achieved in a short time with less consumption of electric power.