发明名称 PEDESTAL CLAMPING CIRCUIT
摘要 PURPOSE:To prevent distortion in an output signal or an error in the next processing circuit occurring by extending a clamping pulse setting its leading or trailing edge which becomes the forefront of a synchronizing signal pulse as an origin longer than an on-going one by the width of the synchronizing signal pulse. CONSTITUTION:The clamping pulse with prescribed width setting the leading or trailing edge of the forefront of the synchronizing signal pulse as the origin is inputted to a clamping circuit 8, and the electric charge of a coupling capacitor is discharged, then, the DC component of an image signal is reproduced. since the width of the clamping pulse outputted from a one-shot circuit 51 is decided by a time constant element assembled in the one-shot circuit 51, it is set at the pulse width within which the trailing edge of the clamping pulse can be housed in a back porch. Therefore, the clamping pulse can be added on the clamping circuit 8 earlier and longer than the on-going one. In such a way, it is possible to obtain a pedestal clamping circuit in which no distortion in the output signal or no error in the next processing circuit occurs.
申请公布号 JPH02158280(A) 申请公布日期 1990.06.18
申请号 JP19880312679 申请日期 1988.12.09
申请人 MITSUBISHI ELECTRIC CORP 发明人 YOSHIMOTO YASUHIRO
分类号 H04N5/18;H03K5/00;H03K5/007 主分类号 H04N5/18
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