| 摘要 |
PURPOSE:To eliminate the wiring region occupying a wide area such as an LCA and to attain high density and high circuit integration by programming a data required for a readout string designation means, a gate circuit selection means and a write cell designation means in advance, and applying a desired logic circuit processing. CONSTITUTION:The circuit has constituents of a gate matrix 1 and a node data matrix 2. The gate matrix 1 is a 4 row and 4 column matrix comprising an AND gate circuit and a NAND gate circuit, and a node data matrix 2 is a RAM in which lots of memory cells each capable of writing and reading out of 1-bit information are formed as a matrix. When a combination circuit comprising gate circuits arranged in n-stage is formed, a data in response to the attained combination circuit is stored to the read string designation means, the gate circuit selection means and the write cell designation means. Thus, the wide area in the wiring region like a logic cell array(LCA) is not required and high density and high circuit integration are attained. |
