| 摘要 |
PURPOSE:To make it in asymmetric LDD structure with high precision, to make the gate length below 0.5mum, and to realize high current capability of a transistor under low power source voltage by giving a smaller inclination than that of the sidewall on the drain region side to the sidewall on the source region side of a gate electrode, and giving a circular arc to the sidewall. CONSTITUTION:A gate oxide film 2 and an impurity 3 are formed on a substrate 1, and a polycrystalline silicon film 4 is overlaid on the gate oxide film 2. Next, this silicon film 4 is patterned so as to form gate electrodes 5 and 6. At this time, the left-hand sidewall of the gate electrode 5 is almost vertical, and right-hand sidewall and the left-hand sidewall of the gate electrode 6 are greatly inclined and are circular. And with the gate electrodes 5 and 6 as masks a low concentration impurity layer 7 is formed. Next, after accumulation of a silicon oxide film, by reactive ion etching sidewall spacers 8 and 9 are formed only at the sidewalls of the gate electrodes. Hereby, it is made into one whose right and left spacer lengths are different. Subsequently, with these spacers 8 and 9 and gate electrodes 5 and 6 as masks ion implantation is done so as to form a high concentration impurity layer 10. Hereafter, by the usual method an insulating layer is formed, and a contact hole is opened and wiring is performed. |
