发明名称 OUTPUT BUFFER CIRCUIT FOR CMOS SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To suppress power noise and to reduce power consumption by outputting a high level through an N-channel MOS transistor(TR), outputting a low level through a P-channel MOS TR, and decreasing an output amplitude by a sum of threshold levels of the gate. CONSTITUTION:With an N-channel MOS TR 2 turned on, a high level is outputted and with a P-channel MOS TR 3 turned on, a low level is outputted. The low level is a voltage given from a gate potential (VG) + a gate threshold voltage (VTP) of the P-channel MOS TR 3, and the high level is a voltage given from the gate potential (VG) - a gate threshold voltage (VTN) of the N-channel MOS TR 2. Thus, even if the voltage VG is given as a ground potential or a power supply potential, the output amplitude of the final stage buffer is reduced by a level of VTN + VTP than heretofore. Thus, power noise is suppressed and the power consumption is reduced.
申请公布号 JPH02158213(A) 申请公布日期 1990.06.18
申请号 JP19880312443 申请日期 1988.12.09
申请人 NEC CORP 发明人 MATSUBA TERUO
分类号 H01L21/8238;G11C11/409;H01L27/092;H03K17/687;H03K19/003;H03K19/0185;H03K19/0948 主分类号 H01L21/8238
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